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78p2351r serial 155m nrz to cmi converter data sheet page: 1 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 august 2006 description the 78p2351r is teridians second generation line interface unit (liu) for 155 mbit/s electrical sdh interfaces (stm1e). the device is a single chip solution that includes an integrated clock & data recovery in both the transmit and receive paths for easy, cost efficient nrz to cmi conversion. the device interfaces to 75 ? coaxial cable through wideband transformers an d can handle over 12.7db of cable loss. by eliminating the needs for synchronous clocks, the small 78p2351r (7x7mm mlf package) is ideal for new stm1e (es1) small form-factor pluggable (sfp) transceiver modules. applications ? stm1e sfp modules ? sdh/atm line cards ? add drop multiplexers (adms) ? pdh/sdh test equipment ? digital microwave radios ? multi-service switches features ? itu-t g.703 compliant, adjustable cable driver for 155.52 mbps cmi-coded coax transmission ? integrated adaptive cmi equalizer and cdr in receive path handles over 12.7db of cable loss ? lvpecl-compatible system interface with integrated cdr in transmit path for flexible nrz to cmi conversion ? configurable via hw control pins or 4-wire serial port interface ? compliant with ansi t1.105.03-1994; itu-t g.813, g.825, g.958; and telcordia gr-253- core for jitter performance ? receive loss of signal (rx los) detection ? receive monitor mode handles up to 20db of flat loss (at max 6db cable loss) ? optional fixed backplane equalizer compensates for up to 1.5m of trace ? operates from a single 3.3v supply ? available in a small 7x7mm 56-pin qfn package ? industrial temperature: -40 ? c to +85 ? c block diagram tx disable td + td - rd + rd - rx los 75ohm coax (cmi encoded) cmi endec cdr adaptive eq. 78p2351r lvpecl data (nrz encoded) fixed eq. cdr downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 2 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 table of cont ents ................................................................................................ 2 functional de scription........................................................................................ 4 reference clock ................................................................................................................ ............4 receiver o peration ............................................................................................................. ..........4 receiver m onitor mode .......................................................................................................... ........4 receive loss of signal ........................................................................................................ .........4 transmitter operation .......................................................................................................... ......5 plesiochron ous mode ............................................................................................................ ........5 synchronou s mode ............................................................................................................... .........5 clock synt hesizer.............................................................................................................. .............5 pulse amplitude adjustment..................................................................................................... ....6 transmit backpla ne equalizer ................................................................................................... ...6 power-down function ........................................................................................................... ......6 loopback modes ................................................................................................................. ............6 power-on reset ................................................................................................................ ..............7 serial control interf ace ...................................................................................................... ...7 register desc ription............................................................................................. 8 register addressing............................................................................................................ .........8 register table................................................................................................................. ................8 legend ......................................................................................................................... ........................9 global registers ...........................................................................................................................9 address 0-0: master control re gister .........................................................................9 port-specific registers ............................................................................................................10 address 1-0: mode control re gister ...........................................................................10 address 1-1: signal control re gister.........................................................................11 address 1-2: advanced tx control regi ster 1 .........................................................11 address 1-3: advanced tx control regi ster 0 .........................................................12 address 1-4: reserved......................................................................................................... 12 address 1-5: status monitor re gister.........................................................................12 address 1-6, 1- 7: reserved...................................................................................................13 pin descri ption ....................................................................................................... 14 legend ......................................................................................................................... ......................14 transmitte r pi ns ............................................................................................................... ............14 receiver pins .................................................................................................................. ................14 reference and st atus pins ...................................................................................................... 14 control pins .................................................................................................................. ................15 serial-port pins ............................................................................................................... .............16 power and gr ound pins .......................................................................................................... ...16 downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 3 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 table of contents (continued) electrical speci fications ................................................................................. 17 absolute maximu m ratings....................................................................................................... ...17 recommended operat ing condit ions ......................................................................................17 dc character istics............................................................................................................. ............17 analog pins c haracteristics .................................................................................................... .18 digital i/o char acteristics.................................................................................................... ......18 pins of type ci, cid ........................................................................................................................18 pins of type cit ..............................................................................................................................1 8 pins of type cis ..............................................................................................................................1 8 pins of type coz ............................................................................................................................18 pins of type po ............................................................................................................................... 19 pins of type pi ............................................................................................................................... ..19 pins of type od ............................................................................................................................... 19 reference clock ch aracteris tics..........................................................................................19 serial-port timing characteris tics........................................................................................20 transmitter specifications for cmi in terface .................................................................21 transmitter ou tput ji tter ...................................................................................................... ....24 receiver specifications for cmi in terface (transform er-coupled) ..................................25 receiver jitte r toler ance ...................................................................................................... ....26 receiver jitter tran sfer func tion .........................................................................................27 loss of signal conditions ...................................................................................................... .....28 application in formation .................................................................................... 28 external co mponents ............................................................................................................ .......28 transformer spec ificat ions ..................................................................................................... .28 thermal info rmation ............................................................................................................ .........28 mechanical specif ications ............................................................................... 29 package info rmation .......................................................................................... 30 ordering information ............................................................................................................ 30 revision history ............................................................................................................................... .........31 downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 4 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 functional description the 78p2351r contains all the necessary transmit and receive circuitry for connection between 155.52mbit/s nrz data sources (sts-3/stm-1) and cmi encoded electrical interfaces (es1/stm-1e). the 78p2351r system interface mimics a 3.3v optical transceiver module and only requires a reference clock and wideband transformer to complete the electrical interface. the chip can be controlled via control pins or serial port register settings. in hardware mode (pin control) the spsl pin must be low. additionally, the following unused pins must be set accordingly: sdo pin must be tied low sdi pin must be tied low sen pin must be tied high in software mode (spsl pin high), control pins set register defaults upon power-up or reset. the 78p2351r can then be configured via the 4-wire serial control interface. see pin descriptions section for more information. reference clock the 78p2351r requires a reference clock supplied to the ckrefp/n pins. for reference frequencies of 19.44mhz or 77.76mhz, the device accepts a single ended cmos level input at ckrefp (with ckrefn pin tied to ground). for reference frequency of 155.52mhz, the device accepts a differential lvpecl clock input at ckrefp/n. the frequency of this reference input is selected by either the cksl control pin or register bit as follows: cksl pin cksl[1:0] bits reference frequency low 0 0 19.44mhz float 1 0 77.76mhz high 1 1 155.52mhz receiver operation the receiver accepts an itu-t g.703 compliant cmi encoded signal at 155.52mbit/s from the rxp/n inputs. when properly terminated and transformer- coupled to the line, the receiver can handle over 12.7db of cable loss. the receivers jitter tolerance exceeds all relevant standards even with 12.7db worth of cable attenuation and inter-symbol interference (isi). see receiver jitter tolerance section for more info. the recovered cmi signal first enters an agc and an adaptive equalizer designed to overcome inter- symbol interference caused by long cable lengths. the variable gain differential amplifier automatically controls the gain to maintain a constant voltage level output regardless of the input voltage level. the outputs of the data comparators are connected to the clock recovery circuits. the clock recovery system employs a delay locked loop (dll), which utilizes a line-rate reference frequency derived from the clock applied to the ckrefp/n pins. after the clock and data have been recovered, the data is decoded to binary by the cmi decoder. the sodp/n pins output the recovered nrz data at lvpecl levels. receiver monitor mode the sck_mon pin or mon register bit puts the receiver in monitor mode and adds approximately 20db of flat gain to the receive signal before equalization. rx monitor mode can handle 20db of flat loss typical of monitoring points with up to 6db (typical 225ft) of cable loss. note that loss of signal detection is disabled during rx monitor mode. receive loss of signal detect the 78p2351r includes a loss of signal (los) detector. when the peak value of the received signal is less than approximately 19db below nominal for approximately 110 ui, receive loss of signal is asserted. the rx los signal is cleared when the received signal is greater than approximately 18db below nominal for 110 ui. during rx los conditions, the receive clock will remain on the last phase tap of the rx dll outputting a stable clock while the receive data outputs are squelched and held at logic 0. note : rx loss of signal detection is disabled during local loopback and receive monitor modes. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 5 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 transmitter operation the transmitter section generates an adjustable itu-t g.703 compliant analog signal for transmission through a wideband transformer onto 75 ? coaxial cable. differential nrz data is input to the 78p2351r on the sidp/n pins at lvpecl levels and passed to a low jitter clock and data recovery circuit. an optional clock decoupling fifo is provided to decouple the on chip and off chip clocks. the nrz data is encoded using cmi line coding to ensure an adequate number of transitions. each of the transmit timing modes can be configured in hw mode or sw mode as shown in the table below. hw control sw control tx mode ckmode smod[1:0] reserved low 0 0 synchronous (fifo enabled) floating 1 0 plesiochronous high 0 1 loop-timing n/a 1 1 plesiochronous mode plesiochronous mode represents a common condition where a synchronous reference clock is not available. in this mode, the 78p2351r will recover the transmit clock from the plesiochronous data and bypass the internal fifo and re-timing block. this mode is commonly used for mezzanine cards, modules, and any application where the reference clock cant always be synchronous to the transmit source clock/data tdk 78p2351r framer/ mapper nrz nrz system clock sodp/n sidp/n ckrefp rxp/n cmip/n xfmr xfmr cmi cmi coax coax xo figure 1: plesiochronous mode synchronous mode when the nrz transmit data is source synchronous with the reference clock applied at ckrefp/n as shown in figure 2, the 78p2351r can be optionally used in synchronous mode or re-timing mode. in this mode, the 78p2351r will recover the clock from the nrz data input and re-time the data in an integrated +/- 4-bit fifo. tdk 78p2351r framer/ mapper nrz nrz system reference clock sodp/n sidp/n ckrefp/n rxp/n cmip/n xfmr xfmr cmi cmi coax coax figure 2: synchronous since the reference clock and transmit clock/data go through different delay paths, it is inevitable that the phase relationship between the two clocks can vary in a bounded manner due to the fact that the absolute delays in the two paths can vary over time. the transmit fifo allows long-term clock phase drift between the tx clock and system reference clock, not exceeding +/- 25.6ns, to be handled without transmit error. if the cl ock wander exceeds the specified limits, the fifo w ill over or under flow, and the ferr register signal will be asserted. this signal can be used to trigger an interrupt. this interrupt event is automatic ally cleared when a fifo reset (frst) pulse is applied, and the fifo is re- centered. notes : 1) external remote loo pbacks (i.e. loopback within framer) are not possible in synchronous operation (fifo enabled) unless the data is re-justified to be synchronous to the system reference clock or the 78p2351r is configured for loop- timing operation. 2) during ic power-up or transmit power-up, the clocks going to the fifo may not be stable and cause the fifo to overflow or underflow. as such, the fifo should be manually reset using frst anytime the transmitter is powered-up. clock synthesizer the transmit clock synthesizer is a low-jitter pll that generates a 311.04 mhz clock for the cmi encoder. a synthesized 155.52 mhz reference clock is also used in both the receive and transmit sides for clock and data recovery. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 6 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 pulse amplitude adjustment contact tdk applications for information on user programmable registers with up to 200mv of programmable transmit gain. transmit backplane equalizer an optional fixed lvpecl equalizer is integrated in the transmit path for architectures that use lius on active interface cards. the fixed equalizer can compensate for up to 1.5m of trace and can be enabled by the txout1 pin or txeq bit as follows: txout1 pin txeq bit tx equalizer low 1 enabled float 0 disabled power-down function power-down control is pr ovided to allow the 78p2351r to be shut o ff. transmit and receive power-down can be set independently through sw control. global power-down is achieved by powering down both the transmitter and receiver. note : the 4-wire serial port interface and configuration registers are not affected by power- down. the transmitter can also be powered down using the txpd control pin. the cmi outputs are tri-stated during transmit power-down for redundancy applications. the txpd pin is active in both hardware and software modes. loopback modes in sw mode, llbk and rlbk bits in the signal control register are provided to activate the local and remote analog loopback modes respectively. in hw mode, the lpbk pin can be used to activate local and remote analog loopback paths as shown in the table below. lpbk pin loopback mode low normal operation float remote (analog) loopback : recovered receive clock and data looped back directly to the transmit driver. the cmi decoder and most of transmit path is bypassed (including the redundant tx monitor output) high local (analog) loopback : transmit clock and data looped back to receiver at the analog media interface. td + td - rd +rd - cmi endec cdr adaptive eq. fixed eq. cdr line-side figure 3: remote (analog) loopback td + td - rd +rd - cmi endec cdr adaptive eq. fixed eq. cdr figure 4: local (analog) loopback in sw mode only, a full remote (digital) loopback bit flbk is also available in the advanced tx control register. this lo opback exercises the entire rx and tx paths of the 78p2351 including the tx clock recovery unit. as such, the user must enable either plesiochronous or loop-timing transmit modes to utilize the full remote (digital) loopback. td + td - rd +rd - cmi endec cdr adaptive eq. fixed eq. cdr line-side figure 5: remote (digital) loopback downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 7 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 internal power-on reset power-on reset (por) function is provided on chip. roughly 50 s after vcc reaches 2.4v at power up, a reset pulse is internally generated. this resets all registers to their default values as well as all state machines within the tran sceiver to known initial values. the reset signal is also brought out to the porb pin. the porb pin is a special function analog pin that allows for the following: ? override the internal por signal by driving in an external active low reset signal; ? use the internally generated por signal to trigger other resets; ? add external capacitor to slow down the release of power-on reset (approximately 8 s per nf added). note : do not pull-up the porb pin to vcc or drive this pin high during power-up. this will prevent the internal reset generator from resetting the entire chip and may result in errors. serial control interface the serial port controlled register allows a generic controller to interface with the 78p2351r. it is used for mode settings, diagnostics and test, retrieval of status and performance information, and for on-chip fuse trimming during prod uction test. the spsl pin must be high in order to use the serial port. the serial interface consists of 4 pins: serial port enable (sen), serial clock (sck_mon), serial data in (sdi), serial data out (sdo). the sen pin initiates the read and write operations. it can also be used to select a particular device allowing sck_mon, sdi and sdo to be bussed together. sck_mon is the clock input that times the data on sdi and sdo. data on sdi is latched in on the rising-edge of sck_mon, and data on sdo is clocked out using the falling edge of sck_mon. sdi is used to insert mode, address, and register data into the chip. address and data information are input least significant bit (lsb) first. the mode and address bit assignment and register table are shown in the following section. sdo is a tristate capable ou tput. it is used to output register data during a read operation. sdo output is normally high impedance, and is enabled only during the duration when register data is being clocked out. read data is clocked out least significant bit (lsb) first. if sdi coming out of the micro-controller chip is also tristate capable, sdi and sdo can be connected together to simplify connections. the maximum clock frequency for register access is 20mhz. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 8 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 register description register addressing address bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port address sub-address read/ write assignment pa[3] pa[2] pa[1] pa[ 0] sa[2] sa[1] sa[0] r/w* register table a) pa[3:0] = 0 : global registers sub addr reg. name description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 mscr (r/w) master control -- <0> -- <0> -- <0> cksl[1] cksl[0] -- -- srst <0> 1 -- (r/w) reserved -- <0> -- <0> -- <1> -- <0> -- <0> -- <0> -- <1> -- <1> 2 -- (r/w) reserved -- -- -- -- -- -- -- -- <0> b) pa[3:0] = 1 : port-specific registers sub addr reg. name description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 mdcr (r/w) mode control pdtx <0> pdrx <0> -- <0> smod[1] smod[0] mon <0> -- <0> -- <1> 1 sgcr (r/w) signal control tcmiinv <0> rcmiinv <0> losor <0> rlbk <0> llbk <0> -- <0> -- <0> frst <0> 2 acr1 (r/w) advanced tx control 1 -- <0> -- <0> -- <0> -- <0> -- <0> -- <0> tpk <0> txeq <0> 3 acr0 (r/w) advanced tx control 0 -- <1> -- <0> -- <1> -- <0> -- <1> bst[1] <0> bst[0] <0> flbk <0> 4 -- (r/w) reserved -- <1> -- -- -- <0> -- <0> -- <0> -- <0> -- <0> 5 stat (r/c) status monitor -- -- -- rxlos -- -- txlos ferr 6-7 -- reserved -- -- -- -- -- -- -- -- downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 9 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 register description (continued) legend type description type description r/o read only r/w read or write r/c read and clear global registers address 0-0: master control register bit name type dflt value description 7:5 -- r/w 0x0 reserved. 4:3 cksl [1:0] r/w x reference clock frequency select : selects the reference clock frequency input at ckrefp/n pins. 11: 155.52 mhz (differential lvpecl input) 10: 77.76 mhz (single-ended cmos input) C tie ckrefn to ground . 00: 19.44 mhz (single-ended cmos input) C tie ckrefn to ground . note : default values depend on the cksl pin setting upon reset or power up. 2:1 -- r/w x0 reserved. 0 srst r/w 0 register soft-reset : when this bit is set, all registers are reset to their default values. this register bit is self-clearing. address 0-1: reserved bit name type dflt value description 7:0 -- r/w 00100x11 reserved. address 0-2: reserved bit name type dflt value description 7:0 -- r/w xxxxxxx0 reserved. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 10 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 register description (continued) port-specific registers for pa[3:0] = 1 only. accessing a regi ster with port address greater t han 1 constitutes an invalid command, and the read/write operation will be ignored. address 1-0: mode control register bit name type dflt value description 7 pdtx r/w 0 transmitter power-down : 0 : normal operation 1 : power-down. cmi transm it output is tri-stated. 6 pdrx r/w 0 receiver power-down : 0 : normal operation 1 : power-down 5 -- r/w 0 reserved. 4 smod[1] r/w x 3 smod[0] r/w x serial mode interface selection : smod[1] smod[0] 0 0 reserved 1 0 synchronous data is passed through the cdr and then through the fifo. 0 1 plesiochronous data is passed through the cdr to recover a clock, but the fifo is bypassed because the data is not synchronous with the reference clock. 1 1 loop timing mode enable : the recovered receive clock is used as the reference for the transmit dll and fifo. note : default values depend on the ckmode pin setting upon reset or power up. 2 mon r/w 0 receive monitor mode enable : 0: normal operation 1: adds 20db of flat gain to the receive signal before equalization. 1:0 -- r/w 01 reserved. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 11 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 register description (continued) address 1-1: signal control register bit name type dflt value description 7 tcmiinv r/w 0 transmit cmi inversion : this bit will flip the polarity of the transmit cmi data outputs at cmip/n. for debug use only. 0: normal 1: invert 6 rcmiinv r/w 0 receive cmi inversion : this bit will flip the polarity of the receive cmi data inputs at rxp/n. for debug use only. 0: normal 1: invert 5 losor r/w 0 receive loss of signal override/disable : when set, the los signal will always remain low. 0: normal 1: forces los output to be low and resets counter 4 rlbk r/w 0 3 llbk r/w 0 analog loopback selection : rlbk llbk 0 0 normal operation 1 0 remote loopback enable : recovered receive data is looped back to the transmit driver for retransmission. 0 1 local loopback enable : the transmit data is looped back and used as the input to the receiver. 2:1 -- r/w 00 reserved. 0 frst r/w 0 fifo reset : 0: normal operation 1: reset fifo pointers to default locations. this reset should be initiated anytime the transmitter or ic powers up to ensure the fifo is centered after internal vco clocks and external transmit clocks are stable. note : fifo reset not required for plesiochronous mode address 1-2: advanced transmit control register 1 bit name type dflt value description 7:1 -- r/w 000000 0 reserved. 0 txeq r/w 0 transmit fixed equalizer enable : when enabled, compensates for between 0.75m and 1.5m of fr4 trace to the lvpecl data inputs sidp/n 0: normal operation 1: enable equalizer downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 12 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 register description (continued) address 1-3: advanced transmit control register 0 bit name type dflt value description 7:3 -- r/w 10101 reserved. 2:1 bst[1:0] r/w 00 transmit driver amplitude boost : adds 5% or 10% of boost to the cmi output. 00 : normal amplitude 01 : 5% boost 10 : reserved 11 : 10% boost 0 flbk r/w 0 full remote (digital) loopback enable : when enabled the recovered receive data is decoded and looped back to the transmit clock recovery unit exercising the entire receive and transmit paths. note : must be used in conjunction with plesiochronous mode or loop- timing mode. address 1-4: reserved bit name type dflt value description 7:0 -- r/w 1xx00000 reserved. address 1-5: status monitor register bit name type dflt value description 7:5 -- r/c xxx reserved. 4 rxlos r/c x receive loss of signal indication : 0: normal operation 1: loss of signal condition detected at cmi inputs 3:2 -- r/c x reserved. 1 txlos r/c x transmit loss of signal indication : 0: valid transmit input signal detected at sidp/n 1: no valid signal detected at sidp/n 0 ferr r/c x transmit fifo error indication : this bit is set whenever the internal ferr signal is asserted, indicating that the fifo is operating at its dept h limit. it is reset to 0 when the frst bit is asserted. 0: normal operation 1: transmit fifo phase error downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 13 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 address 1-6: transmit gain register bit name type dflt value description 7:0 rsvd r/o 0 reserved for pulse amplitude pr ogrammability. contact teridian applications support for more information. address 1-7: reserved bit name type dflt value description 7:0 rsvd r/o 0 reserved for test. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 14 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 pin description legend type description type description a analog pin po lvpecl-compatible differential output cit 3-state cmos digital input od open-drain output ci cmos digital input pi lvpecl-compatible differential input cid cmos digital input w/ pull-down s supply cis cmos schmitt trigger input g ground coz cmos tristate digital output transmitter pins name pin type description sidp sidn 4 5 pi transmit serial data input : differential nrz data input. see transmitter operation section for more info on different timing modes. cmip cmin 53 54 a transmit serial cmi data output : a cmi encoded data signal conforming to the relevant itu-t g.703 pulse templates when properly terminated and transformer coupled to 75ohm cable. notes : 1) pins are tri-stated during tr ansmit power-down. 2) pins are active, but undefined during reset. receiver pins name pin type description sodp sodn 13 14 po receive serial nrz data output : recovered serial data decod ed into nrz format and output at lvpecl levels. notes : 1) outputs are squelched during los and held low. 2) pins are active, but undefined during reset. rxp rxn 50 51 a receive serial cmi input : receive inputs that should be differentially terminated and transformer coupled to the coaxial cable. reference and status pins name pin type description ckrefp ckrefn 45 44 pi/ ci reference clock input : (required) a reference clock input used for clock/data recovery and generation. can be a differential 155.52mhz differential lv pecl input (type pi) at ckrefp/n or a single-ended 19.44mhz or 77. 78mhz cmos input (type ci) at ckrefp (tie ckrefn to ground when unused). los 33 od loss of signal (active-high): standards compatible loss of signal indicator. porb 36 a power-on reset (active low): see power-on reset description on use of this pin. do not pull-up to vcc. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 15 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 pin description (continued) control pins name pin type description lpbk 10 cit loopback selection : low : normal operation float : remote loopback enable: recovered receive data and clock are looped back to the transmitter for retransmission. high : local loopback enable: the transmit data is looped back and used as the input to the receiver. ckmode 9 cit clock mode selection : low : reserved float : reference clock is synchronous to transmit data. clock is recovered with a cdr and data is passed through a fifo high : reference clock is plesiochronous to transmit data. clock is recovered with a cdr and the fifo is bypassed txout1 56 cit advanced tx control 1 : low : enables fixed lvpecl equalizer at the transmit inputs sidp/n (for fr4 trace lengths up to 1.5m). float : normal operation high : normal operation txout0 1 cit advanced tx control 0 : low : nominal amplitude float : 5% amplitude boost high : 10% amplitude boost txpd 8 cid transmitter power down : when high, powers down and tri-states the transmit driver. spsl 32 cid serial port selection : when high, chip is software controlled through the 4-wire serial port. cksl 34 cit reference clock frequency selection : selects the reference frequency that is su pplied at the ckrefp/n pins. its level is read in at power-up or on the rising edge of a reset signal at the porb pin. low : 19.44mhz float : 77.76mhz high : 155.52mhz downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 16 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 pin description (continued) serial-port pins name pin type description sen 41 ciu [spsl=1] serial-port enable : high during read and write operations. low disables the serial port. while sen is low, sdo remains in high impedance state, and sdi and sck activities are ignored. [spsl=0] reserved. must be tied high sck_mon 42 cis [spsl=1] serial clock : controls the timing of sdi and sdo. [spsl=0] receive monitor mode enable : when high, adds 20db of flat gain to the incoming signal before equalization. sdi 40 ci [spsl=1] serial data input : inputs mode and address information. also inputs register data during a write operation. both address and data are input least significant bit first. [spsl=0] reserved. must be tied low sdo 39 coz [spsl=1] serial data output : outputs register information during a read operation. data is output least significant bit first [spsl=0] must be tied low power and ground pins it is recommended that all supply pins be connected to a single power supply plane and all ground pins be connected to a single ground plane. name pin type description vcc 2, 6, 11, 31, 38, 43, 48, 52 s power supply (vdd) gnd 3, 7, 12, 30, 35, 37, 46, 47, 49, 55 g ground downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 17 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications absolute maximum ratings operation beyond these limits may permanently damage the device. parameter rating supply voltage (vdd) -0.5 to 4.0 vdc storage temperature -65 to 150 c junction temperature -40 to 150 c pin voltage (cmip,cmin) vdd + 1.5 vdc pin voltage (all other pins) -0.3 to (vdd+0.6) vdc pin current 100 ma recommended operating conditions unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges. parameter rating dc voltage supply (vdd) 3.15 to 3.45 vdc ambient operating temperature -40 to 85c junction temperature -40 to 125c dc characteristics: parameter symbol conditions min nom max unit supply current (including transmitter current through transformer) idd max cable length 160 180 ma receive-only supply current iddr transmitter disabled (pdtx=1) 92 106 ma power down current iddq pdtx=1, pdrx=1 7 10 ma downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 18 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) analog pins characteristics: the following table is provided for informat ive purpose only. not tested in production. parameter symbol conditions min nom max unit rxp and rxn common-mode bias voltage vblin ground reference 1.9 2.6 v rxp and rxn differential input impedance rilin 20 k ? analog input/output capacitance cin 8 pf porb input impedance -- 5 k ? digital i/o characteristics: pins of type ci, cid: parameter symbol conditions min nom max unit input voltage low vil 0.8 v input voltage high vih 2.0 v input current iil, iih -1 0 1 a pull-down resistance rpd type cid only 40 58 120 k ? input capacitance cin 8 pf pins of type cit: parameter symbol conditions min nom max unit input voltage low vtil 0.4 v input voltage high vtih vcc-0.6 v minimum impedance to be considered as float state rtiz 30 k ? pins of type cis: parameter symbol conditions min nom max unit low-to-high threshold vt+ 1.3 1.7 v high-to-low threshold vt- 0.8 1.2 v input current iil, iih -1 1 a input capacitance cin 8 pf pins of type coz: parameter symbol conditions min nom max unit output voltage low vol iol = 8ma 0.4 v output voltage high voh ioh = -8ma 2.4 v output transition time tt c l = 20pf, 10-90% 2 ns effective source impedance rscr 30 ? tri-state output leakage current iz -1 1 a downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 19 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) digital i/o characteristics: (continued) pins of type po: parameter symbol conditions min nom max unit signal swing vpk 0.5 0.8 1.1 v common mode level vcm vdd referenced -1.55 -1.2 -1.1 v effective source impedance reff 20 ? rise time tr 10-90% 0.8 1.2 ns fall time tf 10-90% 0.8 1.2 ns pins of type pi : parameter symbol conditions min nom max unit signal swing vpki 0.3 v common mode level vcm vdd referenced -1.6 -1.2 -0.8 v pins of type od parameter symbol conditions min nom max unit output voltage low vol iol = 8ma 0.4 v pull-down leakage current ipd logic high output 1 na pull-up resistor rpu 4.7 10 k ? reference clock characteristics: parameter symbol conditions min nom max unit ckref duty cycle -- 40 60 % synchronous mode -20 +20 ckref frequency stability -- plesiochronous or loop-timing mode. (see note 1) -75 +75 ppm note 1 : in plesiochronous mode, the transmit data source (i.e. framer) must still be of +/-20ppm quality in order to meet sonet/sdh bit rate requirements. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 20 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) serial-port timing characteristics: parameter symbol conditions min typ max unit sdi to sck setup time tsu 4 ns sdi to sck hold time th 4 ns sck to sdo propagation delay tprop 10 ns sck frequency sck 20 mhz 1 sa0 sa1 sa2 pa0 pa1 pa2 pa3 z cs sck sdi sdo t su t h x x or z t su t h d0 d1 d2 d3 d4 d5 d6 d7 z t prop figure 6: read operation figure 7: write operation 0 sa0 sa1 sa2 pa0 pa1 pa2 pa3 d0 d1 d2 d3 d4 d5 d6 d7 z cs sck sdi sdo t su t h x x t su t h downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 21 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) transmitter specifications for cmi interface bit rate : 155.52mbits/s 20ppm code : coded mark inversion (cmi) relevant specification : itu-t g.703, telcordia gr-253, ansi t1.102 with the coaxial output port driving a 75 ? load, the output pulses conform to the templates in figures 8 and 9. these specifications are tested during production test . consult application note for reference schematic, layout guidelines, and recommended transformers. parameter condition min nom max unit peak-to-peak output voltage (fuse-trimmed to nominal target at final test) template, steady state 0.9 1.04 1.1 v rise/ fall time 10-90% 2 ns negative transitions -0.1 0.1 positive transitions at interval boundaries -0.5 0.5 transition timing tolerance positive transitions at mid- interval -0.35 0.35 ns the following specifications are not tested during pro duction test. they are included for information only. note that the return loss depends on the board layout and the particular transformer used. parameter condition min nom max unit output impedance driver is open drain 1 8 m ? pf return loss 7mhz to 240mhz 15 db downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 22 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) (note 1) (note 1) (note 1) 0.600.55 0.50 0.45 0.40 0.05 -0.05-0.50 -0.55 -0.60 -0.45 -0.40 (note 1) 0.35ns nominal zero level (note 2) t = 6.43ns 0.1ns 0.1ns 1ns 1.608ns 1.608ns 1.608ns 1.608ns 1ns 1ns 1ns 0.1ns 0.1ns 1ns 1ns nominal pulse 0.35ns v note 1 C the maximum steady state amplitude should not exceed the 0.55v limit. overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55v and 0.6v, provided that they do not exceed the steady state level by more than 0.05v. note 2 C for all measurements using these masks, the signal should be ac coupled, using a capacitor of not less than 0.01 f, to the input of the oscilloscope used for measurements. the nominal zero level for both masks should be aligned with the oscilloscope trace wit h no input signal. with the signal then applied, the vert ical position of the trace can be adjusted with the objective of meeting the limi ts of the masks. any such adjustment should be the same for both masks and should not exceed 0.05v. this may be checked by removing the input signal again and verifying that the trace lies with 0.05v of the nominal zero level of the masks. note 3 C each pulse in a coded pulse sequence should meet the limit s of the relevant mask, irrespective of the state of the pre ceding or succeeding pulses, with both pulse masks fixed in the same relati on to a common timing reference, i.e. with their nominal start and finish edges coincident. the masks allow for hf jitter caused by intersym bol interference in the output stage, but not for jitter pres ent in the timing signal associated with the source of the interface signal. w hen using an oscilloscope technique to determine pulse compliance w ith the mask, it is important that successive traces of the pulses overlay in order to suppress t he effects of low frequency jitter. this can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the meas ured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. note 4 C for the purpose of these masks, the rise time and decay time should be measured between C0.4v and 0.4v, and should not exceed 2ns. figure 8 C mask of a pulse corresponding to a binary zero. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 23 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) (note 1) (note 1) 0.600.55 0.50 0.45 0.40 0.05 -0.05-0.50 -0.55 -0.60 -0.45 -0.40 (note 1) nominal zero level (note 2) 6.43ns 0.1ns 0.1ns 1ns 1.608ns 1ns nominal pulse v 3.215ns 1.2ns 1.2ns 3.215ns 1.608ns 1ns 1ns 0.5ns 0.5ns note 1 C the maximum steady state amplitude should not exceed the 0.55v limit. overshoots and other transients are permitted to fall into the shaded area bounded by the amplitude levels 0.55v and 0.6v, provided that they do not exceed the steady state level by more than 0.05v. note 2 C for all measurements using these masks, the signal should be ac coupled, using a capacitor of not less than 0.01 f, to the input of the oscilloscope used for measurements. the nominal zero level for both masks should be aligned with the oscilloscope trace wit h no input signal. with the signal then applied, the vert ical position of the trace can be adjusted with the objective of meeting the limi ts of the masks. any such adjustment should be the same for both masks and should not exceed 0.05v. this may be checked by removing the input signal again and verifying that the trace lies with 0.05v of the nominal zero level of the masks. note 3 C each pulse in a coded pulse sequence should meet the limit s of the relevant mask, irrespective of the state of the pre ceding or succeeding pulses, with both pulse masks fixed in the same relati on to a common timing reference, i.e. with their nominal start and finish edges coincident. the masks allow for hf jitter caused by intersym bol interference in the output stage, but not for jitter pres ent in the timing signal associated with the source of the interface signal. w hen using an oscilloscope technique to determine pulse compliance w ith the mask, it is important that successive traces of the pulses overlay in order to suppress t he effects of low frequency jitter. this can be accomplished by several techniques [e.g. a) triggering the oscilloscope on the meas ured waveform or b) providing both the oscilloscope and the pulse output circuits with the same clock signal]. note 4 C for the purpose of these masks, the rise time and decay time should be measured between C0.4v and 0.4v, and should not exceed 2ns. note 5 Cthe inverse pulse will have the same characteristics, noting that the timing tolerance at the level of the negative and positive transitions are 0.1ns and 0.5ns respectively. figure 9 C mask of a pulse corresponding to a binary one downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 24 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) transmitter output jitter the transmit jitter specification ensures compliance with itu-t g.813, g.823, g.825 and g.958; ansi t1.102- 1993 and t1.105.03-1994; and gr-253-core for all support ed rates. transmit output jitter is not tested during production test. parameter condition min nom max unit transmitter output jitter 200 hz to 3.5 mhz, measured with respect to ckref for 60s 0.075 uipp transmitter output jitter detector measured jitter a mplitude f1 f2 20db/decade downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 25 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) receiver specifications for cmi interface (transformer-coupled) consult application notes for reference schematic, layout guidelines, and recommended transformers. parameter condition min typ max unit peak differential input amplitude, rxp and rxn mon=0. 12.7db of cable loss 70 550 mvpk peak differential input amplitude, rxp and rxn mon=1. 20db flat loss with 6db cable loss (max) 25 80 mvpk flat-loss tolerance mon=0. all valid cable lengths. -2 4 db latency 5 10 ui pll lock time 1 10 s return loss 7mhz to 240mhz 15 db the input signal is assumed compliant with itu-t g.703 and can be attenuated by th e dispersive loss of a cable. the minimum cable loss is 0db and the maximum is C12.7db at 78mhz. the worst case line corresponds to the itu-t g.703 recommendation. the typical line corresponds to a typical installation referred to in ansi t1.102-1993. t he receiver is tested using the cable model. it is a lumped element approximation of the worst case line. 0 5 10 15 20 25 30 1.00e+05 1.00e+06 1.00e+07 1.00e+08 1.00e+09 frequency (hz) attenuation (db) worst case typical figure 10: typical and worst-case cable attenuation downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 26 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) receiver jitter tolerance the 78p2351r exceeds all relevant jitter tolerance specif ications shown in figure 11. stm-1e (electrical) jitter tolerance specifications ar e in itu-t g.825. receive jitter tolerance is not tested during production test. 0.01 0.1 1 10 100 1.e+00 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz 155mbps electrical (cmi) interfaces g.825 - stm-1e tolerance (for 2048 kbps networks) g.825 - stm-1e tolerance (for 1544 kbps networks) jitter frequency jitter tolerance ( uipp ) figure 11: jitter tolerance - electrical (cmi) interfaces parameter condition min nom max unit 10hz to 19.3hz 38.9 uipp 19.3hz to 500hz 750 f-1 s 500hz to 6.5khz 1.5 uipp 6.5khz to 65khz 9800 f-1 s stm-1e jitter tolerance 65khz to 1.3mhz 0.15 uipp downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 27 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) receiver jitter transfer function the receiver clock recovery loop filter characteristics such that the receiver has the following transfer function. the corner frequency of the rx dll is approximately 120 khz. receiver ji tter transfer function is not tested during production test. -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1.00e+03 1.00e+04 1.00e+05 1.00e+06 1.00e+07 figure 12: jitter transfer parameter condition min nom max unit receiver jitter transfer function below 120 khz 0.1 db jitter transfer function roll-off 20 db per decade downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 28 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 electrical specifications (continued) loss of signal condition parameter condition min typ max unit los threshold -35 -19 -15 db los timing 10 110 255 ui nominal value maximum cable loss loss of signal must be cleared loss of signal must be declared tolerance range los can be detected or cleared 3 db 15db 35db application information external components: component pin(s) value units tolerance receiver termination resistor rxp rxn 75 ? 1% transmitter termination resistor cmip cmin 75 ? 1% transformer specifications: component value units tolerance turns ratio for the receiver 1:1 turns ratio for the transmitter (center-tapped) 1:1ct suggested manufacturers: halo, mi nicircuits, tamura, belfuse thermal information: package conditions ja ( ? c/w) jc ( ? c/w) no forced air; 4-layer jedec test board 46.8 16.6 standard 56-pin jedec qfn no forced air; 4-layer jedec test board die attach pad soldered to pcb 23.5 15.6 schematics for reference schematics, layout guidelines, suggested tr ansformer part numbers, etc. please check teridian semiconductor's website or contact your local sales re presentative for the latest application note(s) and/or evaluation boards. downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 29 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 mechanical specifications top view 1 7.000 0.05 max 0.90 max 0 =12 side view seating plane 0.23 0.05 0.40 bottom view 1 0 . 4 0 0 0 . 1 0 0 5.200 2.55 0.075 2.55 0.075 3.500 3.375 3.375 3.500 6.750 6.750 6.750 5.200 5.10 0.15 0.25 min. 5.10 0.15 56-pin quad flat no-lead package (qfn) (all dimensions in mm) downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 30 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 package information (top view) 1 txout0 vcc gnd sidp sidn vcc gnd txpd ckmode lpbk vcc sodp sodn sck_monsen sdi sdo vcc gnd porb gnd cksl los spsl vcc gnd n/c n/cn/c n/c n/c n/c n/c n/cn/c n/c n/c n/c n/c n/c n/c cmin cmip vcc rxn rxp gnd vcc gnd gnd ckrefp txou1 ckrefn vcc gnd gnd 78p2351r-im 56 15 29 43 14 28 42 23 4 5 6 7 8 9 13 12 11 10 4140 39 38 37 36 35 34 30 31 32 33 55 44 52 50 49 48 51 53 54 46 45 47 ordering information part description order number package mark 56-pin qfn; revision a06 78p2351r-im 78p2351r-im xxxxxxxxxxp6 tape & reel option append r n/a lead-free option append /f xxxxxxx-xxx xxxxxxxxxxp6f downloaded from: http:///
78p2351r serial 155m nrz to cmi converter page: 31 of 31 ? 2006 teridian semiconductor corporation rev. 2.1 revision history -- contact teridian for revision history of earlier releases v2-0 august 15, 2005: final datasheet release updated ordering numbers to reflect production silicon revision a06 improved/modified functional descriptions improved/modified register descriptions added flbk bit removed rx lol bit improved/modified pin descriptions updated electrical specification min/max limits for: dc characteristics, cid, ciu, cit, and po pin types cmi loss of signal conditions changed name and logo from tdk to teridian v2-1 august 15, 2006: updated ordering numbers to remove silicon revision a06 updated package mark from c6 to p6 if and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of ord er acknowledgment, including those pertaining to warranty, patent in fringement and limitation of liability. teridian semiconduct or corporation (tsc) reserves the right to make changes in specifications at any time without notic e. accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. ts c assumes no liability for applications assistance. teridian semiconductor corp., 6440 oak canyon rd., irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http://www.teridian.com downloaded from: http:///

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